CV

Education

M.S. in Integrated Circuit Engineering, Southeast University, 2029 (Expected)
B.S. in Integrated Circuit Design and Integrated System, Fuzhou University, 2026

February–May 2026: Design of MAC16 Based on Domestic Digital EDA System
- Fuzhou University
- A radix-4 Booth encoding scheme is employed, combined with a 4-2 compressor tree and hybrid adder, to reduce the number of partial products from 16 to 9 through three-stage compression. The 16×16-bit unsigned multiplier is partitioned into four 8×8 multiplication modules according to input timing, and a multi-cycle path design methodology is adopted to meet the 1 GHz frequency requirement. In addition, the multiplier core is reused to achieve area optimization, resulting in a compact layout of 90×90 μm², while effectively resolving the mismatch between computation throughput and output data rate.
Oct–Dec 2024: Designed a 64-bit unsigned carry-lookahead adder (CLA) in SMIC 0.18μm process.
- Fuzhou University
- Using Cadence Virtuoso, a radix-4 Kogge-Stone tree with three levels of dot-operation layers was selected. The design includes block carry generate (G) and block carry propagate (P) circuits, with 2/3/4-bit dot-operation cells to cover the full 64-bit output range. Carry units (AND-OR gates) and sum units (XOR gates) were implemented to realize parallel-prefix computation. Inputs and outputs are latched through D flip-flops to ensure data stability, achieving a delay of 1.15 ns.